// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.8.0.115.3
// Netlist written on Sun May 07 21:41:02 2017
//
// Verilog Description of module gates
//

module gates (a, b, led, empty) /* synthesis syn_module_defined=1 */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(28[8:13])
    input a;   // d:/git/oschina/step_mxo2/labs/src/gates.v(41[9:10])
    input b;   // d:/git/oschina/step_mxo2/labs/src/gates.v(41[11:12])
    output [5:0]led;   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    output [7:0]empty;   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    
    
    wire a_c, b_c, led_c_5, led_c_3, led_c_1, n22, VCC_net, n23, 
        GND_net, n24;
    
    VLO i31 (.Z(GND_net));
    OB led_pad_4 (.I(n22), .O(led[4]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    OB led_pad_5 (.I(led_c_5), .O(led[5]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    LUT4 z_5__I_0_13_i2_1_lut_2_lut (.A(a_c), .B(b_c), .Z(led_c_1)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(56[14:17])
    defparam z_5__I_0_13_i2_1_lut_2_lut.init = 16'h9999;
    OB led_pad_1 (.I(led_c_1), .O(led[1]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    LUT4 a_I_0_15_2_lut_rep_3 (.A(a_c), .B(b_c), .Z(n24)) /* synthesis lut_function=(A+(B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(54[14:17])
    defparam a_I_0_15_2_lut_rep_3.init = 16'heeee;
    OB led_pad_2 (.I(n24), .O(led[2]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    OB led_pad_3 (.I(led_c_3), .O(led[3]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    OB led_pad_0 (.I(n23), .O(led[0]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(47[16:19])
    OB empty_pad_7 (.I(VCC_net), .O(empty[7]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_6 (.I(VCC_net), .O(empty[6]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_5 (.I(VCC_net), .O(empty[5]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_4 (.I(VCC_net), .O(empty[4]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_3 (.I(VCC_net), .O(empty[3]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_2 (.I(VCC_net), .O(empty[2]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_1 (.I(VCC_net), .O(empty[1]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    OB empty_pad_0 (.I(VCC_net), .O(empty[0]));   // d:/git/oschina/step_mxo2/labs/src/gates.v(46[17:22])
    IB a_pad (.I(a), .O(a_c));   // d:/git/oschina/step_mxo2/labs/src/gates.v(41[9:10])
    IB b_pad (.I(b), .O(b_c));   // d:/git/oschina/step_mxo2/labs/src/gates.v(41[11:12])
    GSR GSR_INST (.GSR(VCC_net));
    LUT4 z_5__I_0_13_i4_1_lut_2_lut (.A(a_c), .B(b_c), .Z(led_c_3)) /* synthesis lut_function=(!(A+(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(54[14:17])
    defparam z_5__I_0_13_i4_1_lut_2_lut.init = 16'h1111;
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 a_I_0_16_2_lut_rep_2 (.A(a_c), .B(b_c), .Z(n23)) /* synthesis lut_function=(!(A (B)+!A !(B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(56[14:17])
    defparam a_I_0_16_2_lut_rep_2.init = 16'h6666;
    LUT4 z_5__I_0_13_i6_1_lut_2_lut (.A(a_c), .B(b_c), .Z(led_c_5)) /* synthesis lut_function=(!(A (B))) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(52[14:17])
    defparam z_5__I_0_13_i6_1_lut_2_lut.init = 16'h7777;
    LUT4 a_I_0_14_2_lut_rep_1 (.A(a_c), .B(b_c), .Z(n22)) /* synthesis lut_function=(A (B)) */ ;   // d:/git/oschina/step_mxo2/labs/src/gates.v(52[14:17])
    defparam a_I_0_14_2_lut_rep_1.init = 16'h8888;
    VHI i32 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

